1. Field of the Invention
The present invention relates to methods of driving an organic electroluminescence emission portion.
2. Description of the Related Art
In an organic electroluminescence display device (hereinafter simply referred to as “an organic EL display device” for short when applicable) using an organic electroluminescence element (hereinafter simply referred to as “an organic EL element” for short when applicable) as an electroluminescence element, a luminance of the organic EL element is controlled in accordance with a value of a current caused to flow through the organic EL element. Also, a simple matrix system and an active matrix system are well known as a driving method in the organic EL display device as well similarly to the case of a liquid crystal display device. Although the active matrix system has a disadvantage that a structure is more complicated than that based on the simple matrix system, it has various advantages that an image having a light luminance is obtained, and so forth.
A drive circuit composed of five transistors and one capacitor (called a 5Tr/1C drive circuit) is well known as a circuit for driving an organic electroluminescence emission portion (hereinafter simply referred to as “an electroluminescence portion” when applicable) constituting the organic EL element from Japanese Patent Laid-Open No. 2006-215213. As shown in FIG. 16, the 5Tr/1C drive circuit is composed of five transistors of a write transistor TRW, a drive transistor TRD, a first transistor TR1, a second transistor TR2 and a third transistor TR3, and one capacitor portion C1. Here, a source/drain region on one side of the drive transistor TRD constitutes a second node ND2, and a gate electrode of the drive transistor TRD constitutes a first node ND1.
For example, each of the write transistor TRW, the drive transistor TRD, the first transistor TR1, the second transistor TR2, and the third transistor TR3 is composed of an n-channel thin film transistor (TFT), and the electroluminescence portion ELP is provided on an interlayer insulating film or the like which is formed so as to cover the drive circuit. An anode electrode of the electroluminescence portion ELP is connected to the source/drain region on the one side of the drive transistor TRD. On the other hand, a voltage VCat (for example, 0 V) is applied to a cathode electrode of the electroluminescence portion ELP. In FIG. 16, reference symbol CEL designates a capacitance of the drive transistor TRD.
As shown in a conceptual view of FIG. 17, the organic EL display device includes:
(1) a scanning circuit 101;
(2) a signal outputting circuit 102;
(3) (M×N) organic EL elements each including the electroluminescence portion ELP, and a drive circuit for driving the electroluminescence portion ELP;
(4) M scanning lines SCL which are each connected to the scanning circuit 101 and which extend in a first direction;
(5) N data lines DTL which are each connected to the signal outputting circuit 102 and which extend in a second direction different from the first direction (specifically, in a direction intersecting perpendicularly to the first direction);
(6) a power source portion 100;
(7) a first transistor controlling circuit 111;
(8) a second transistor controlling circuit 112; and
(9) a third transistor controlling circuit 113.
Here, the N organic EL elements 10 are disposed in the first direction, and the M organic EL elements are disposed in the second direction, that is, the (M×N) organic EL elements 10 are disposed in a two-dimensional matrix. It is noted that although the (3×3) organic EL elements 10 are shown in FIG. 17 for the sake of convenience, this is merely an exemplification.
FIG. 18 schematically shows a timing chart in the drive operation in the organic EL elements 10. Also, FIGS. 19A to 19I schematically show an ON/OFF state and the like of the write transistor TRW, the drive transistor TRD, the first transistor TR1, the second transistor TR2, and the third transistor TR3. As shown in FIG. 18, preprocessing for executing threshold voltage canceling processing is executed for [time period-TP(5)1]. That is to say, each of potentials of a second transistor controlling line AZ2 and a third transistor controlling line AZ3 is set at a high level in accordance with the operations of the second transistor controlling circuit 112 and the third transistor controlling circuit 113. As a result, as shown in FIG. 19B, the second transistor TR2 and the third transistor TR3 are each turned ON, so that a potential at the first node ND1 is set at V0fs (for example, 0 V). On the other hand, a potential at the second node ND2 is set at Vss (for example, −10 V). As a result, a difference in potential between the gate electrode of the drive transistor TRD, and the source/drain region on the electroluminescence portion ELP side becomes equal to or higher than the threshold voltage Vth (for example, 3 V) of the drive transistor TRD. Also, the drive transistor TRD is held in an ON state.
Next, as shown in FIG. 18, the threshold voltage canceling processing is executed for [time period-TP(5)2]. The potential of the second transistor controlling line AZ2 is set at a low level in and before completion of [time period-TP(5)1], thereby turning OFF the second transistor TR2 as shown in FIG. 19C. A potential of a first transistor controlling line CL1 is set at a high level in accordance with the operation of the first transistor controlling circuit 111 in a commencement of [time period-TP(5)2] while the ON state of the third transistor TR3 is maintained. As a result, as shown in FIG. 19D, the first transistor TR1 is turned ON. As a result, the potential at the second node ND2 changes toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential at the first node ND1. That is to say, the potential at the second node ND2 held in a floating state rises. Also, when the difference in potential between the gate electrode and the source/drain region on the electroluminescence portion ELP side of the drive transistor TRD reaches the threshold voltage Vth of the drive transistor TRD, the drive transistor TRD is turned OFF. In this state, the potential at the second node ND2 is held approximately at (V0fs−Vth). After that, for [time period-TP(5)3], while the third transistor TR3 is held in the ON state, the potential of the first transistor controlling line CL1 is set at the low level in accordance with the operation of the first transistor controlling circuit 111. As a result, as shown in FIG. 19E, the first transistor TR1 is turned OFF. Next, for [time period-TP(5)4], the third transistor controlling line AZ3 is set at the low level in accordance with the operation of the third transistor controlling circuit 113, thereby turning OFF the third transistor TR3 as shown in FIG. 19F.
Next, as shown in FIG. 18, processing for writing data to the drive transistor TRD is executed for [time period-TP(5)5]. Specifically, as shown in FIG. 19G, while each of the first transistor TR1, the second transistor TR2 and the third transistor TR3 is held in the OFF state, a potential of corresponding one of the data lines DTL is set at a voltage [a voltage of a video signal (a drive signal, a luminance signal) VSig used to control the luminance in the electroluminescence portion ELP] corresponding to a video signal. Next, the potential of the corresponding one of the scanning lines SCL is set at the high level, thereby turning ON the write transistor TRW. As a result, the potential at the first node ND1 rises to VSig. The electric charges based on a change in potential at the first node ND1 are distributed to the capacitor portion C1, the capacitance CEL of the electroluminescence portion ELP, and the parasitic capacitance between the gate electrode and the source/drain region on the electroluminescence portion ELP side of the drive transistor TRD. Therefore, the potential at the second node ND2 changes so as to follow a change in potential at the first node ND1. However, the change in potential at the second node ND2 becomes small as the capacitance value of the capacitance CEL of the electroluminescence portion ELP becomes larger. In general, the capacitance value of the capacitance CEL of the electroluminescence portion ELP is larger than that of each of the capacitor portion C1, and the parasitic capacitance of the drive transistor TRD. Then, when it is assumed that the potential at the second node ND2 hardly changes, a difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TRD is expressed by Expression (1):Vgs≈VSig−(V0fs−Vth)   (1)
After that, as shown in FIG. 18, mobility correcting processing is executed for [time period-TP(5)6]. In the mobility correcting processing, the potential at the source/drain region on the electroluminescence portion ELP side of the drive transistor TRD (that is, the potential at the second node ND2) is made to rise in accordance with the characteristics (such as the magnitude of a mobility μ) of the drive transistor TRD. Specifically, as shown in FIG. 19H, while the write transistor TRW is held in the ON state, the first transistor TR1 is turned ON in accordance with the operation of the first transistor controlling circuit 111. Next, after a lapse of a predetermined time (t0), the write transistor TRW is turned OFF. As a result, when the value of the mobility μ of the drive transistor TRD is large, an amount, ΔV (potential correction value), of potential risen at the source/drain region on the electroluminescence portion ELP side in the drive transistor TRD becomes large. On the other hand, when the value of the mobility μ of the drive transistor TRD is small, an amount, ΔV (potential correction value), of potential risen at the source/drain region on the electroluminescence portion ELP side in the drive transistor TRD becomes small. Here, the difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TRD is transferred from Expression (1) into Expression (2):Vgs≈VSig−(V0fs−Vth)−ΔV   (2)
It is noted that a predetermined time (a total time t0 of [time period-TP(5)6] demanded to execute the mobility correcting processing has to be previously calculated as a design value when the organic EL display device is designed.
By performing the above operations, the threshold voltage canceling processing, the write processing and the mobility correcting processing are all completed. Also, for subsequent [time period-TP(5)7], the write transistor TRW is held in the OFF state, and the first node ND1, that is, the gate electrode of the drive transistor TRD is held in the floating state. On the other hand, the first transistor TR1 is held in the ON state, and thus one of the source/drain regions of the first transistor TR1 is held in a state of being connected to a power source portion (a voltage VCC, for example, 20 V) for controlling the electroluminescence of the electroluminescence portion ELP. Therefore, as the result of the foregoing, as shown in FIG. 18, the potential at the second node ND2 rises, so that the same phenomenon as that in a so-called bootstrap circuit occurs in the gate electrode of the drive transistor TRD. Thus, the potential as well at the first node ND1 rises. As a result, the difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TRD holds the value in Expression (2). In addition, a current caused to flow through the electroluminescence portion ELP is a drain current Ids caused to flow from the drain region into the source region of the drive transistor TRD. Thus, when it is assumed that the drive transistor TRD ideally operates in a saturated region, the drain current Ids can be given by Expression (3):Ids=k·μ·(Vgs−Vth)2=k·μ·(Vgs−Vth−ΔV)2   (3)
As shown in FIG. 19I, the drain current Ids is caused to flow through the electroluminescence portion ELP. Also, the electroluminescence portion ELP emits a light with a luminance corresponding to the value of the drain current Ids.